SMART EDA EMPOWERMENT
FORMAL VERIFICATION
TOOLS
01 / TRUSTED
We reduce risk for decision makers and engineers in the chip design and hardware manufacturing industry.
02 / INSIGHTFUL
Gain relevant insights and make better decisions right from the beginning and throughout the whole design process.
03 / RESULT DRIVEN
Our formal verification software enables tangible results. We call this smart verification empowerment.
FPGA DESIGN
TOOLS
01 / FLEXIBLE
One portable tool for many FPGA architectures, with an extensible software platform that works well for small and large FPGA devices, simple 4-LUT architectures and complex ones with challenging hard-IP blocks. Our open and flexible software platform is the ideal basis for evaluating experimental FPGA architectures.
02 / INNOVATIVE
We bridge the gap between industry and academia, by providing a software platform that supports current industry FPGA architectures and at the same time has open interfaces that enable academics to develop tomorrow's P&R algorithms right on the hardware that matters in real-world applications.
03 / RESULT DRIVEN
The flexibility of our platform enables us to use just the right algorithm for every target device. The openness allows us to integrate improvements developed by academics and open source contributors alike, constantly improving quality of results for all users of our platform.
ON-SITE & ONLINE
TRAINING
01 / APPROACHABLE
Get to know the basic concepts of Formal Verification using both the Open Source Yosys formal verification tool suite and our commercial-grade Symbiotic EDA Suite.
02 / HANDS-ON
Our 16 hours course covers not only the basic formal verification properties, such as assume and assert, but also the more advanced operators used to frame them, $past, $rase, $global_clock, etc.
03 / EMPOWERED
You will examine several real-world examples during the course. These include basic counters, a serial peripheral interface (SPI) port, as well as the formal properties necessary for a bus interface.
